True Circuits has also been working closely with other leading silicon foundries and IDMs on the porting and silicon testing of its PLLs and DLLs in their 65nm processes.
"Our continued focus on R&D and our proven design methodology allow us to quickly and reliably port our designs to advanced processes so our customers have the high-performance timing IP they will need to accelerate their 65nm product development," remarked Stephen Maneatis, True Circuits, CEO. "We have licensed 65nm PLLs and DLLs to a number of key TSMC customers during the last year and are seeing strong demand for our industry-leading timing technologies across a number of industry segments."
True Circuits' 65nm PLL and DLL designs are based on TCI's industry-leading analog timing circuits that have been used in hundreds of customer products in 0.25um to 90nm processes with many different foundries and IDMs.
TCI has extensively characterized this new line of PLL and DLL hard macros for optimal 65nm performance and continues to engage with key partners and customers in the development and silicon testing of test chips and pre-production products.
True Circuits PLLs are available in a range of frequencies, multiplication factors (1-4096), sizes and functions. Each features the company's LockNow!(TM) Technology to dramatically improve PLL lock times. This is a significant advantage for chips that need fast restarts from low-power modes.
True Circuits DLLs delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature. They are available in different sizes and form factors and are ideal for high-speed DDR interface applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in TSMC, UMC and CHRT processes from 0.18um to 65nm. The hard macros are available for a per use license fee with reuse options and no royalty fees. The license fee includes integration support from TCI to ensure a successful customer tape out. The deliverables include GDSII and LVS Spice netlists, behavioral and synthesis models, Library Exchange Format (LEF) files and extensive user documentation.