Compared to existing FPGA-based solutions, the SN65LVDS324 lowers the bill-of-materials (BOM) by 20 percent, reduces system power consumption by more than 10 percent and shrinks package size by 50 percent. It provides full HD, 1080p60 image quality in a host of video capture applications, including surveillance IP cameras and video conferencing systems, as well as industrial, consumer and professional video recording equipment.

The new SN65LVDS324 includes key features such as an optimised solution for sensor-to-processor interface. As a dedicated bridge for video streams between HD image sensors and processors, the SN65LVDS324 lowers BOM costs by up to 20 percent compared to existing FPGA-based solutions.

It includes a dedicated sensor-to-processor interface, which means that In 1080p60 system implementations, the SN65LVDS324 typically consumes less than 150 mW, reducing system power consumption by more than 10 percent versus current FPGA solutions.

This latest TI image sensor receiver chip set is delivered in the smallest package sized form factor. The dedicated functionality provides a 50-percent smaller package than current FPGAs on the market.

It is designed to provide excellent video resolution and supports a wide range of resolutions and frame rates, up to 1080p60-full-HD to maximize system performance.

The SN65LVDS324 is an extension of TI's popular Flatlink and Flatlink 3G serial interface technology, which reduces the number of signal lines used for synchronous parallel data bus structures with no loss in data throughput. It is also optimised to work with a variety of processors, including TI's OMAP and DaVinci processors for video applications.

The SN65LVDS324 is available in a 4.5-mm by 7-mm, 59-ball PBGA (ZQL) package.